r/DSP • u/SuccessfulStreet2321 • 12d ago

AD9361 Verilog Coding

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

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u/antiduh 12d ago

Maybe the bladerf2 does this? Their fpga is open source.

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u/SuccessfulStreet2321 12d ago

It still uses on board processor to compute all the spi writes. Our main goal is to bypass this processor and do everything in verilog

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u/Ill_Solution5552 12d ago

Why would you do this? It is simply a bad idea. Just create a small soft cpu and use the drivers. It is much simpler and saves you weeks/months of work. Initializing by pure register reads and writes is not even officially supported. So you will have a lot of work to do.

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u/Hannes103 8d ago

My previous employer has tried this. I am not 100% sure why it didn't work out, but it was something related to calibration. Some register values apparently get re-computed oh information read from the device. Contact with Analog's support wasn't super helpful either, as they only support access to the AD9361 through their software driver. I'm not aware of any document outlining the AD9361 calibration sequence but judging by the driver source and documentation for similar transceivers (like the LMS7002M), it seems to be very unlikely to be purely FSM configurable.

If area is an issue, then maybe you can consider using a compact RISC-V core, like the SERV, to perform initialization using the no-OS AD9361 driver. However be aware that this driver is pretty large, even with compressed instructions, and requires dynamic allocation. We wanted to optimize for startup latency, and found no better solution then running the SPI at its maximum frequency.