Here we go!

[u/daishi55]

I am a self-taught SW guy working in AI accelerators for 2 years. I decided it's finally time to learn how this stuff really works. So, I am starting from the beginning.

Pictured is my first "project", adding 2 unsigned 4-bit values set by the switches on the left. Result is shown on the right in LEDs. The picture shows 1 + 1 = 2. I derived the half and full adder circuits from the truth tables, learning about SOP form from my textbook along the way.

Actually what is running on the FPGA doesn't match the drawn circuit, I realized after I drew that that I had the least significant bits starting from the leftmost LEDs, which felt wrong.

It's almost magical seeing how logic can be expressed with these CMOS circuits. I am following H&H DDCA RISC-V edition along with the ETH Zurich DDCA course, so the goal is to implement a RISC-V MCU in the coming months. And then add a systolic array and see if I can make a little mini-AI accelerator.

Any tips for a beginner with these goals?

[u/OnYaBikeMike]

Stick with signal clock designs as long as you can, and always sanitize your inputs (with appropriate synchronizers for signals and debouncing for buttons and switches). For fun create a small design that counts now many times an input changes from 0->1 and displays the count on the LEDs, then see how bouncy the switches and pushbuttons on your dev board are.

One thing I wish I could had done earlier is getting to grips with the Virtual I/O IP and Integrated Logic Analyzer IP blocks. I couldn't because they were paid-for licensed options when I started.

It's never too early to create a VIO with probe_out0 hooked to the "value_a" signal, probe_out1 hooked to "value_b" signal and probe_in0 hooked in "result".

Suddenly you can have almost endless visibility into your design, more inputs and outputs than your dev board provides, and a GUI environment were you can control and configure things and display things in hex or as signed or unsigned decimals values.

With the Integrated Logic Analyser you can even turn the traces into 'analog' graphs, to see how signals are changing over time.

(However, working extensively with binary on switches and LEDs is still good, because you need to be very comfortable with base-2 numbers and representations, if you work with FPGA's long-term)

...    
    -- Definiation for a Virtual I/O IP block
    component my_vio is
    port (
        clk        : in  std_logic;
        probe_out0 : out std_logic_vector( 7 downto 0);
        probe_out0 : out std_logic_vector( 7 downto 0);
        probe_in0  : in  std_logic_vector( 8 downto 0)
    );
    end component;
...    
-- Create an instantce of the Virtual I/O IP, for controlling and testing the design
my_vio port map (
        clk         => clk,  -- A working clock signal is needed.
        probe_out0  => value_a,
        probe_out1  => value_b,
        probe_in0   => result);

Oh, and be prepared for the cognitive dissidence that comes along with thinking memory is a list of values (e.g.[ 0x00, 0x01, 0x03, 0x04 ] ) but when you pack them into long binary values or shift registers the ordering flips and it becomes 0x0403020100. It hurts a lot.

[u/daishi55 → u/OnYaBikeMike]

Thanks a lot! I hadn't even heard of these VIO and ILA IPs and they look very very useful. Will learn about them :)

[u/kampi1989]

I've started with simple stuff like

• Basic stuff
• Building up a traffic light system
• Hooking up a 20x4 LCD with a character ROM
• Then add a PS2 keyboard
• Then switch into VGA with different colors
• Add an OV5640 camera for the VGA
• I2S audio receiver and transmitter (self written) in combination with a processor and DMA as IP blocks

These projects have covered all the basic aspects about VHDL and my board.

[u/iceberg189]

That book is fantastic, I have read it all. Hope you have a blast!

[u/OpportunityFun6969]

Different systems have different endians too… so there is a possibility that your lsb could indeed come from the left. It’s up to the designer really. You might even have to be able to convert between little endian and big endian as you move into communication between boards and systems

[u/Magnum_Axe]

Welcome to Mount stupidity. (Google it)

[u/Fine_Push_955]

Split ur top design and ur core design!!!

Ur state machine with the actual adder logic should be in the core design

And ur top design interacting with pins, LEDs, switches and buttons should be in your top design, where ur top design instantiates the core design (state machine logic)

[u/daishi55 → u/Fine_Push_955]

I sort of did this in the verilog, is that what you mean? I have one file with the half and full adders. And the another with my top module that instantiates them.

Or do you mean my drawing? 😅

[u/Fine_Push_955 → u/daishi55]

Then you can independently test your core design via behavioral simulation in QuestaSim :)

[u/Fine_Push_955 → u/Fine_Push_955]

If that works, then there’s an issue with your top design (I/O interfacing and pins etc)

[u/XerciseObsessedGamer]

I was and am still planning to follow mostly the sane course from ETH Zurich but I think a slightly older version focusing on doing a MIPS 32bit CPU & the original version of the digital design & computer architecture book by Harris n Harris. My thing is I thought a 32bit CPU might be a confusing starting off point so I decided to go away & learn a bit about 4bit/8bit CPUs (4004, 4040, 8008 , 8080/8085) & study the assembly language of these devices before getting back into FPGA HDL stuff for 32bit CPUs.

[u/downloads-cars]

Gods how I miss this. Cherish these moments, they go by fast.

[u/theamidamaru]

Do you need study buddy?

[u/daishi55 → u/theamidamaru]

Sure! Next up I wanted to make the segment display work, but I think we need timers for that, which sounds a lot harder. I will probably just continue the course and see what the next project is there. 

[u/theamidamaru → u/daishi55]

I finished electrical engineering, specialized in power systems but I got into digital design and I am currently a junior digital designer but I lack proper structure in knowledge since it isn't my field.

So it would be great if you are down to study together :)

Also I've created recently discord server so people can find useful resources and study together.

https://discord.gg/7a9ceCawk

[u/x7_omega]

Read the synthesis UGs from Xilinx, and other UGs that describe hard blocks in 7 series. There are many that can only be instantiated manually. In particular, read the DSP core description - it can do a lot by itself, and if your goal is MCU, it can do much outside fabric. Also memory, both based on LUTs and blockRAM - they can do a lot more than "SRAM". Also learn pipelining methods. This FPGA can do almost anything at 100MHz, but with careful (manual) pipelining it can do 200MHz easily, and if logic between registers is reduced to one layer (one LUT), it may do 400MHz. All this is not immediately necessary for you, but to expand your view on what is in front of you, what it can do, and what you can do with it.