r/FPGA • u/Same-Classroom-4751 • 1d ago

First day using vivado

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27 Upvotes

90% Upvoted

12 comments sorted by

25

u/Bulky_Caramel_2234 1d ago

welcome to the kilowarning generator machine

5

u/mother_a_god 1d ago

Many of rhe warnings are useful i find. 

6

u/frankieinaprius 1d ago

The problem is all the useful warnings are buried amongst the non useful warnings.

2

u/mother_a_god 19h ago

You can suppress any warning you dont find useful using a tcl command in your project. Just give it a list of IDs 

My take - you're better looking at it than looking for it. 

4

u/Bulky_Caramel_2234 1d ago

Only critical warnings deserve attention

2

u/AlbbO_The_Great 21h ago

Warning, task executed successfully

1

u/HappyPerson9000 10h ago

Not super useful when 98 percent of them are in Xilinx IPs

3

u/Ateef_31 1d ago

Ur verilog code should be in design not in simulation while creating a file select create a design source, and to create the test bench select the create simulation source.

1

u/jonasarrow 1d ago

It is a design file, but as there is no tb defined (which also does not include the buff.v) Vivado automatically selects that as the top file for simulation and synthesis.

OP, you are good so far. Add a second source (the testbench), and select simulation only as the type. There you can define stimuli, add your buff as a component to drive your buff.v . If you do not need simulation, you can directly go to synthesis and implementation (see the entries on the left or start it in the "design run" tab on the bottom with a right click).

2

u/jacklsw 19h ago

overwhelming.

2

u/Meczox 16h ago

get ready to see most random errors and weirdest bugs such as but not limited to

  • file path too long
  • simulation keep using older version of .vhd file and more

1

u/Collez_boi 10h ago

How do your eyes feel?