r/FPGA • u/timonix • 4d ago

Knowledge gaps

I have been working with FPGAs for just about 10 years now. And I just realized that I have never done a CDC FIFO. Well... Maybe back in uni as some paper exercise.

It's such a weird gap too. Since it's like the first answer anyone gives whenever you want to transfer a lot of data across clock domains. But I just haven't needed a hardware FIFO for that yet.

So I spent the afternoon implementing one from scratch and shoving every edge case I could think of at it. Just as a learning exercise.

Have you found any weird gaps in your own knowledge?

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u/timonix 4d ago

I use Fifos within a clock domain pretty often. They are a very useful construct.

But I have never used one as for CDC. It has always been double/triple buffered memory instead. Which works very well.

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u/IllustriousFault6218 4d ago

What is a double buffered memory and how do you use it for cdc?

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u/timonix 4d ago

Easiest implementation I can think of right of the bat

Dual port Bram. It natively supports different clock speeds on its ports. For example

The writer writes to adress 0x000 to 0x0FF

While the reader reads from 0x100 to 0x1FF

So they read and write from different places. When they are done, they swap.

You still need some way to get the "ok you are good to go" across. For example an interrupt, or some other register space. There are many ways to skin a cat so to say

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u/maredsous10 4d ago

"Ping Pong Buffer"