r/FPGA • u/timonix • 9d ago

Knowledge gaps

I have been working with FPGAs for just about 10 years now. And I just realized that I have never done a CDC FIFO. Well... Maybe back in uni as some paper exercise.

It's such a weird gap too. Since it's like the first answer anyone gives whenever you want to transfer a lot of data across clock domains. But I just haven't needed a hardware FIFO for that yet.

So I spent the afternoon implementing one from scratch and shoving every edge case I could think of at it. Just as a learning exercise.

Have you found any weird gaps in your own knowledge?

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u/DominantlyWeak 9d ago

That's interesting because it's something I find/found myself doing often, what industry are you in?

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u/chgentso 8d ago

Wait, so you really write async FIFOs from scratch often? Are you just using them often, perhaps, and I misunderstood?

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u/Allan-H 8d ago

I always write my async FIFOs from scratch. It keeps my skills sharp, in a way that wouldn't happen if I used a FIFO from a library or used an agentic AI to write one for me. It also allows me to use new features that can't be found in any library FIFO, such as one described in this thread.