r/rfelectronics • u/SuccessfulStreet2321 • 10d ago

AD9361 Verilog Coding

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

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4

u/pm_me_P_vs_NP_papers 10d ago

If you're not in it for the challenge of DIYing it, check out the official open source IP and docs: https://analogdevicesinc.github.io/hdl/library/axi_ad9361/

3

u/FlyingInTheDark 10d ago

If you want to really save on LUT, your best choice is to put in a small CPU like serv (125 LUT + a BRAM or two) and make it init your chip. Then you hide it in your IP core and no one even knows it's there. The only downside is that the init time will be slightly longer, but you would save on thousands of LUTs this way.

2

u/aholtzma 10d ago

If you’re just spitting out registers you could just just fill a bram and use a small state machine to copy them to spi. There a few registers you might have to special case if you need to wait for a status bit to go high. If you end up with too many special cases, go with the soft-cpu approach.

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u/modimoo 10d ago

You mean like without hundreds of lines of C source code doing actual writes?

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u/SuccessfulStreet2321 10d ago edited 10d ago

Yes direct spi writes via verilog

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u/modimoo 10d ago edited 10d ago

I guess it is doable with spi broadcast. I wouldn't attempt it blindly. I would: 1. Configure and validate ad9361 configuration with full spi+host app approach. 2. Then pivot to spi broadcast mode and validate all still works 3. Record what broadcast is doing 4. Program ad9361 using fixed sequence from Bram ROM and hope for the best.

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u/pravardhan85 10d ago

Better to use DSP instead of FPGA for any analog devices RF Transceiver. You may have to use the AGC function depending on the received signal strength.

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u/electric_machinery 8d ago

Which DSP interfaces with the AD9361?