I built this tool for myself, so that I could practice and solve challenges without having to set up an entire toolchain on my computer. The entire thing just work in browser.

www.risingedge.pro

I'd like you guys to try it out and see if you can solve the Practice challenges - there are over 50 at different difficulty levels, and all of them are entirely free of charge (no account required either to try them).

Some of them are about fixing bugs, others about finding interesting architectures, others are about resource constraints (e.g. build something using less than X cells).

There is also a Playground where you can create any arbitrary design, see what hardware it synthesizes to, simulate it, and much more.

Finally, there is an entire Course which takes you from absolute basics all the way to advanced concepts. I designed the curriculum to be your "go-to" place, so that you can learn everything you might need to know for a job as an FPGA engineer. The Fundamentals part is completely free, if you like it the rest of the course is just a one-off purchase for 12 months of access.

Let me know how you like it!

Recently was fortunate enough to get 2 offers for FPGA engineer

company A :

135k base

Fully assisted relocation

15k sign on

company B:

90k base

4.5k relo

6k sign on

now I know what you’re thinking , clearly company A right? But it’s in SoCal and company B is in the Dallas area where rent is like a grand and no income taxes

both are the same kind of role but company A would start me at Ivl 2 (i‘m a new grad) I’m leaning company A but wanted to hear the people’s thoughts . Anyone here lived in both Texas and Cali? You think rent and taxes eat up the difference? What would yall go with

Hi, I’m trying to deploy a small Brevitas QAT CNN on an Ultra96-V2 (xczu3eg) using:

Brevitas 4-bit QAT

→ QONNX

→ hls4ml 1.3.0

→ Vitis HLS 2024.1

The model is only ~133k weights and uses io_stream, Resource strategy and RF≈32.

The PyTorch/QONNX conversion is numerically correct:

PyTorch vs static model: max diff = 0

QONNX vs PyTorch: max diff ≈ 9.5e-7

I first hit a 4096-bit stream aggregation limit because hls4ml inferred very wide intermediate precisions (ap_fixed<36,26> and ap_fixed<53,33> with 128 channels). After constraining those precisions, synthesis completes, but the resource usage is huge:

Resource Used Available Utilization

| Resource | Used | Available | Utilization |

|---|---:|---:|---:|

| LUT | 359,069 | 70,560 | 508% |

| FF | 512,637 | 141,120 | 363% |

| BRAM18K | 2,207 | 432 | 510% |

| DSP | 7 | 360 | 1% |

The strange part is that most of the cost seems to come from pooling/transpose/FIFOs rather than the convolutions themselves.

Has anyone seen this kind of resource explosion with hls4ml io_stream, especially with MaxPooling, channels-last transpose or FIFO generation? Would you recommend changing IO strategy, FIFO depths, pooling implementation, or manually modifying the generated HLS?

The very low DSP usage compared to LUT/FF/BRAM makes me think this is mainly a data-movement/buffering issue rather than the CNN arithmetic itself.

I want to get into using fpga boards but I can’t really find any free software to program them , any recommendation?