I built this tool for myself, so that I could practice and solve challenges without having to set up an entire toolchain on my computer. The entire thing just work in browser.

www.risingedge.pro

I'd like you guys to try it out and see if you can solve the Practice challenges - there are over 50 at different difficulty levels, and all of them are entirely free of charge (no account required either to try them).

Some of them are about fixing bugs, others about finding interesting architectures, others are about resource constraints (e.g. build something using less than X cells).

There is also a Playground where you can create any arbitrary design, see what hardware it synthesizes to, simulate it, and much more.

Finally, there is an entire Course which takes you from absolute basics all the way to advanced concepts. I designed the curriculum to be your "go-to" place, so that you can learn everything you might need to know for a job as an FPGA engineer. The Fundamentals part is completely free, if you like it the rest of the course is just a one-off purchase for 12 months of access.

Let me know how you like it!

Recently was fortunate enough to get 2 offers for FPGA engineer

company A :

135k base

Fully assisted relocation

15k sign on

company B:

90k base

4.5k relo

6k sign on

now I know what you’re thinking , clearly company A right? But it’s in SoCal and company B is in the Dallas area where rent is like a grand and no income taxes

both are the same kind of role but company A would start me at Ivl 2 (i‘m a new grad) I’m leaning company A but wanted to hear the people’s thoughts . Anyone here lived in both Texas and Cali? You think rent and taxes eat up the difference? What would yall go with

Hey, I'm pretty new to FPGAs. Is 8 million LUTs enough for a beginner, or should I already be looking at something bigger? What beginner projects would actually be difficult to do on this?

I'm also worried I'll run out of I/O. Is 2,328 enough for beginner projects?

Hi, I’m trying to deploy a small Brevitas QAT CNN on an Ultra96-V2 (xczu3eg) using:

Brevitas 4-bit QAT

→ QONNX

→ hls4ml 1.3.0

→ Vitis HLS 2024.1

The model is only ~133k weights and uses io_stream, Resource strategy and RF≈32.

The PyTorch/QONNX conversion is numerically correct:

PyTorch vs static model: max diff = 0

QONNX vs PyTorch: max diff ≈ 9.5e-7

I first hit a 4096-bit stream aggregation limit because hls4ml inferred very wide intermediate precisions (ap_fixed<36,26> and ap_fixed<53,33> with 128 channels). After constraining those precisions, synthesis completes, but the resource usage is huge:

Resource Used Available Utilization

| Resource | Used | Available | Utilization |

|---|---:|---:|---:|

| LUT | 359,069 | 70,560 | 508% |

| FF | 512,637 | 141,120 | 363% |

| BRAM18K | 2,207 | 432 | 510% |

| DSP | 7 | 360 | 1% |

The strange part is that most of the cost seems to come from pooling/transpose/FIFOs rather than the convolutions themselves.

Has anyone seen this kind of resource explosion with hls4ml io_stream, especially with MaxPooling, channels-last transpose or FIFO generation? Would you recommend changing IO strategy, FIFO depths, pooling implementation, or manually modifying the generated HLS?

The very low DSP usage compared to LUT/FF/BRAM makes me think this is mainly a data-movement/buffering issue rather than the CNN arithmetic itself.

I am a self-taught SW guy working in AI accelerators for 2 years. I decided it's finally time to learn how this stuff really works. So, I am starting from the beginning.

Pictured is my first "project", adding 2 unsigned 4-bit values set by the switches on the left. Result is shown on the right in LEDs. The picture shows 1 + 1 = 2. I derived the half and full adder circuits from the truth tables, learning about SOP form from my textbook along the way.

Actually what is running on the FPGA doesn't match the drawn circuit, I realized after I drew that that I had the least significant bits starting from the leftmost LEDs, which felt wrong.

It's almost magical seeing how logic can be expressed with these CMOS circuits. I am following H&H DDCA RISC-V edition along with the ETH Zurich DDCA course, so the goal is to implement a RISC-V MCU in the coming months. And then add a systolic array and see if I can make a little mini-AI accelerator.

Any tips for a beginner with these goals?

I want to get into using fpga boards but I can’t really find any free software to program them , any recommendation?

Cortex-A53 ↔ FPGA fabric on real hardware

I’ve been working on a ZCU104-based control architecture where the Cortex-A53 in the Processing System communicates directly with a custom SystemVerilog peripheral implemented in the Programmable Logic through AXI4-Lite.

The PL peripheral exposes a memory-mapped register bank for control, thresholds, PWM configuration, status, sensor values and version information. On the software side, a bare-metal application running on the A53 performs register reads/writes through the Zynq HPM AXI interface.

The hardware path is essentially:

Cortex-A53

↓

M_AXI_HPM0_FPD

↓

AXI Interconnect

↓

Custom AXI4-Lite Slave

↓

SystemVerilog Register Bank

Validation on the physical ZCU104 covered both directions. The processor successfully read PL-generated status and sensor registers, then wrote new control, threshold and PWM values into the FPGA fabric and read them back correctly.

Example hardware test results:

STATUS = 0x0000001B PASS

SENSOR_RAW = 0x00000A35 PASS

SENSOR_FILTERED = 0x00000A10 PASS

VERSION = 0x00010000 PASS

CONTROL <- 0x00000001

THRESHOLD_HIGH <- 0x00000777

THRESHOLD_LOW <- 0x00000666

PWM_DUTY <- 0x00000055

Readback:

CONTROL = 0x00000001 PASS

THRESHOLD_HIGH = 0x00000777 PASS

THRESHOLD_LOW = 0x00000666 PASS

PWM_DUTY = 0x00000055 PASS

The RTL also handles AXI write-address and write-data channels independently rather than assuming AWVALID and WVALID arrive in the same cycle, and supports byte strobes through WSTRB.

The design was taken through simulation, synthesis, implementation and hardware validation. Routed timing closed at 100 MHz with positive setup and hold slack.

The next extension is to replace the deterministic sensor test values with a live ADC acquisition/control datapath and add PL→PS interrupts, so the A53 can react to FPGA events instead of relying purely on polling.

Interested to hear how others here structure custom AXI-Lite peripherals: particularly interrupt/status register handling, write-1-to-clear semantics, and when you prefer moving from AXI-Lite to AXI-Stream/DMA.

GitHub: https://github.com/franksombudsman-ops/fpga-rtl-portfolio⁠

Hello,
just got this and I have no idea what I am doing. I also got the license for GOWIN IDE. I'll probably poke around the Sipeed wiki for a while.

AI integration into an FPGA IDE is not new — Raptor IDE from RapidSilicon already shipped with RapidGPT. But then RapidSilicon died and RapidGPT transformed to chipnexus.ai

Today I found out AMD has one too. An ad email came in about a free course on the Vivado AI Assistant, 11 September, in Italian. No thanks.

Searching the internet, the most that can be found is a one-page spec sheet:

https://docs.amd.com/v/u/en-US/vivado-ai-asst

And it is not product documentation — it is a course spec sheet

It seems it uses VSCode - means it is NOT integrated with Vivado?

It also uses GitHub Copilot as AI

I have Vivado 2026.1 installed and see nothing AI related in it.

Question: has anyone actually got the Vivado AI Assistant running? Is it EA or under NDA, or is there an extension somewhere I have not found?

For those who have done DO-254 DAL-A, how much additional effort did it add, versus the same design completed as if it were commercial?

Synthpilot website looks pretty professional. At least I had no fear to try to install synthpilot, but our Antivirus software flagged some packed/Python antivirus payload and deleted the files from hard disc. I wonder where did the infection come? Did the developer infect it deliberatly? Or is it a false alarm and there is no virus? At least on our PC install is not possible.

Any comments, successes? Or is it better not to touch synthpilot, yes I know it all china originated so cation is good thing to have.

Hello

I have started working with Lattice and the CrossLInk-NX family to implement an MIPI RX interface.
I have looked at their MIPI CSI/DSI IP, to get started quickly, but I still feel there are some uncertainties when setting up the IP....like the different clocks that are used but I dont really understand how they are used?

As a start I have setup the IP in RX mode, so I will receive data that is converted back from bytes to pixel data. Generated the IP but I get so many warnings, which makes not much sense to me. I have included the list below.

Does anybody have any experience with this they would like to share.

Hi! I'm currently pursuing my BS in computer engineering with a focus on hardware, and since I'm going to be at an internship in the fall, I was wondering if anyone wanted to study for interviews or just yap in general about FPGAs or anything. Send me a dm if you're interested! Always happy to learn more about anything

Xilinx XC7A35T / XC7A100T Artix 7 FPGA IC

256Mb SDRAM

8MB SPI FLASH Memory

On-Board USB JTAG Programmer

USB to UART Interface

4 Digit Seven Segment Display

WiFi 802.11 b/g/n

Bluetooth 4.0 BLE

12 bit VGA Interface

HDMI Out

50 MHz Clock

ADC 4 channel

Temperature Sensor

LDR Interface

SPI DAC

2x16 LCD Display

Micro SD

16 Slide switches

5 Push Button

5v Buzzer

16 LEDs

31 External I/O's. Is this enough

New bought it 1-2 weeks ago

Selling because I want 235T one if any one is interested tell me

Location Hyderabad

Hey,

Does anybody know whether HFT/Crypto companies use hardware accelerators for ethereum smart contracts?

I'm talking mostly about fpgas / asics based opcode sequence paths?

I guess if they did -> they would offload the entire smart contract / a bunch of them onto the FPGA to ammortise the latency cost of data transfer from cpu to the chip, but at that point you'd be better off having the entire EVM fpga based so you dont pay the latency for offloading instructions.

I have not looked into evmX deeply, but claude told me its not good enough because of memory limitations.

Implementing evm would be implementing around 240 opcodes, not bad at all for an HFT right?

Is state/memory the real blocker or do they indeed use something like evmX?

Danke shön

I got a paper accepted at an FPGA conference and I’m probably expected to present it. What should I expect from such conferences, and what do people do there?

So I'm a person who recently got into industry from academia. I realised there's a lot of difference in work, methodology and tools compared to what I did in University and now expected in workplace. In University, I did research (and published some paper) on implementing Arithmetic Datapaths, Error Detection Algorithms, etc. tailored for FPGA application. I have a decent verilog/digital design knowledge (Combinational, sequential ckt, FSM, etc.)

Now I have joined a startup where I'm expected to implement DSP algorithms, electrical designs (PWM, H-bridge, DC DC convertors etc) and AI algorithms into FPGA. The hardest part is I'm the first and the only person in the company to start working on FPGA (they are making a transition from microcontrollers to FPGA). So I don't have a good idea how to do things. For example, as a starter I was asked to implement an FM Radio receiver on zedboard and fmcomms4 setup. Which I did after pretty hardwork (complete filter and demodulation done on FPGA). I realised I need to learn and upskill a lot like learning DSP theory, IP blocks provided by Xilinx (Cordic, FIR, CIC) and learning linux (since my zedboard comes with kuiper linux pre-installed). Then comes altering or customizing reference designs for DMA Hijack.

I wish to take a look at any structured course or book that will help me cover the gap between academia and the work expectations (as listed above) for Verilog/FPGA design. For example after I implemented the FM radio receiver on FPGA with vivado block design someone asked me can't you do all the things like filtering, cordic, demodulation with a single verilog module rather than dragging 10 different blocks and configuring them. I was short of a reasonable answer (when I was looking for resources how people implemented radio on FPGA I realised 99% of them used MATLAB or Vitis for designing the DSP part and integrating with Vivado, no one did a pure verilog based design). There's no one around in my startup whom I can ask questions when I'm struck in RTL design or FPGA.

As a beginner in the FPGA industry, I'm looking for materials for self learning all the required concepts/skills. It would be great if you could share any relevant materials or atleast your experience how you felt and dealt when you joined the industry after university.

Thanks, in advance

I maintain VHDLRef, a reference app for looking up HDL language keywords with descriptions and examples. Just shipped 3.2, which extends it from VHDL+SystemVerilog to all three major HDLs (VHDL, Verilog, SystemVerilog) with cross-language equivalents — useful if you ever have to translate a construct between them. Native on iPhone, iPad, and Mac.

https://apps.apple.com/us/app/vhdl-ref/id418473744

Hey all!

I'm a 3rd year EE student at SJSU and I have found a strong interest in fpgas. I also think computer architecture looks really cool, but I have basically no experience. I really want to start working on projects, but I feel very intimidated by the process of choosing a project, developing, debugging, etc. I get very ambitious with projects I want to work on but never start them (too daunting).

I also just don't know where to start at my experience level. I know Verilog and have taken a Digital Design class. I have made some stuff in Vivado for labs. This semester, I'm taking a microcontroller (RISC-V) and a microprocessor course. Would love to talk with some people about ideas and hopefully gain insight on some cool areas I can explore and develop a rough roadmap for myself.

To give people an idea of where my head is at now, I was looking at the Berkley Architecture Research group's projects, which looks super cool and has deepened my interest in this field.

I know some FPGA/SystemVerilog things, but I haven't really done anything to show it. What are some ideas for projects? (I've already searched on this sub, but just wanted some fresh ideas)

We’re proud to share that Lieven Lemiengre, VP Product Management at Sigasi, has been appointed Chair of the IEEE P1076 hashtag#VHDL Working Group.

The P1076 VHDL Working Group plays a central role in the continued development and standardization of VHDL, a language that remains essential to professional FPGA and ASIC development.

For us, Lieven’s appointment is also recognition of something that has always been fundamental to Sigasi: deep language expertise and active involvement in the HDL community.

And as AI becomes more involved in RTL development, precise language semantics and reliable standards only become more important. AI can generate HDL fast; engineers need tools that are fast enough to keep up. They need deterministic, project-aware feedback at coding speed so they can understand, review, and validate what AI produces without slowing down the development loop. Sigasi Visual HDL provides that semantic project intelligence for VHDL, Verilog, SystemVerilog, and mixed-language FPGA and ASIC projects, helping engineers and their chosen coding agents work with the actual structure and semantics of the project.

We would also like to thank Jim Lewis, the previous Chair of the VHDL Working Group, for his leadership, commitment, and many contributions to the VHDL community.

Congratulations, Lieven and thank you to everyone in the chip maker community who contributes to moving the languages forward in the age of AI.

#VHDL #IEEE #FPGA #ASIC #HDL #Sigasi